1. Technical Field
The embodiments herein generally relate to circuit design, and, more particularly, to electrostatic discharge (ESD) protection circuitry used in complementary metal-oxide-semiconductor (CMOS) technology.
2. Description of the Related Art
Protecting electric circuits and devices from ESD continues to be a problem in integrated circuit technology. ESD protection circuits and devices can be used to overcome ESD problems. Typical ESD protection circuitry, such as that described in U.S. Pat. No. 8,059,376 can generally handle a DC voltage up to 7.5v. However, there are certain market segments where a high voltage interface is needed and thus a special ESD protection technique is required. For example, a low noise block (LNB) controller should interface with a 19v DC supply from a cable setup box. Generally, this voltage far exceeds all conventional ESD breakdown limits. Moreover, due to the complexity of the 19v design, there are certain inherent start-up issues which the conventional ESD protection circuits that handle a DC voltage only up to 7.5v do not have to deal with and cannot deal with. Additionally, the conventional approach is to use a high voltage interface circuit, usually manufactured in a bipolar high voltage process, to regulate the voltage down to approximately 3-5 volts as the supply for the LNB controller. However, to minimize the cost of the total system solution, integrating the voltage regulation functionality onto the controller, which is typically manufactured in CMOS technology, is highly desirable.
A conventional ESD protection clamp is illustrated in FIG. 1. A clamp device (M_clamp) is connected between the supply and ground. A resistor/capacitor pair (R_clamp) forms a time lag apparatus to create a time lag when an ESD event occurs on the supply and creates a ground current return path to allow the ESD charge to flow from the supply to ground. This assumes a low and constant voltage level (e.g. up to 7.5v) on the effected device/circuit. However, when the DC voltage increases (e.g., over 7.5v), the ESD device runs the risks of breaking down if no protective measure is undertaken. Therefore, it is desirable to develop ESD protection circuitry that overcomes these challenges.